Power-efficient and highly scalable parallel graph sampling using FPGAs

Usman Tariq, Umer I. Cheema, Fahad Saeed. Power-efficient and highly scalable parallel graph sampling using FPGAs. In International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017. pages 1-6, IEEE, 2017. [doi]

@inproceedings{TariqCS17,
  title = {Power-efficient and highly scalable parallel graph sampling using FPGAs},
  author = {Usman Tariq and Umer I. Cheema and Fahad Saeed},
  year = {2017},
  doi = {10.1109/RECONFIG.2017.8279806},
  url = {https://doi.org/10.1109/RECONFIG.2017.8279806},
  researchr = {https://researchr.org/publication/TariqCS17},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-3797-5},
}