Table of Contents

• Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systemsUmer Farooq, Habib Mehrez, Muhammad Khurram Bhatti. 1-6 [doi]
• LinkBlaze: Efficient global data movement for FPGAsPongstorn Maidee, Alireza Kaviani, Kevin Zeng. 1-8 [doi]
• Flexible and low-cost HSM based on non-volatile FPGAsDiogo Parrinha, Ricardo Chaves. 1-8 [doi]
• Accelerating low rank matrix completion on FPGAShijie Zhou, Rajgopal Kannan, Viktor K. Prasanna. 1-7 [doi]
• Optimal weight storage improves fault tolerance of SOMsBernard Girau, César Torres-Huitzil. 1-6 [doi]
• Continuous live-tracing as debugging approach on FPGAsChristopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck. 1-8 [doi]
• Power-efficient and highly scalable parallel graph sampling using FPGAsUsman Tariq, Umer I. Cheema, Fahad Saeed. 1-6 [doi]
• HGum: Messaging framework for hardware acceleratorsSizhuo Zhang, Hari Angepat, Derek Chiou. 1-8 [doi]
• Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platformLucas B. da Silva, Danilo Almeida, José Augusto Miranda Nacif, Ismael Sanchez-Osorio, Carlos A. Hernandez-Martinez, Ricardo Ferreira. 1-7 [doi]
• Fast generation of high throughput customized deep learning accelerators on FPGAsHanqing Zeng, Chi Zhang, Viktor Prasanna. 1-8 [doi]
• A Dynamically Reconfigurable Automata Processor OverlayRasha Karakchi, Lothrop O. Richards, Jason D. Bakos. 1-8 [doi]
• Adaptive software-augmented hardware reconfiguration with dataflow design automationClaudio Rubattu, Francesca Palumbo, Maxime Pelcat. 1-4 [doi]
• Towards a type 0 hypervisor for dynamic reconfigurable systemsBenedikt Jansen, Fatih Korkmaz, Halil Derya, Michael Hübner, Mário Lopes Ferreira, João Canas Ferreira. 1-7 [doi]
• Evaluation of the CAESAR hardware API for lightweight implementationsPanasayya Yalla, Jens-Peter Kaps. 1-6 [doi]
• Evaluation of CGRA architecture for real-time processing of biological signals on wearable devicesJoao Lopes, Diogo Sousa, João Canas Ferreira. 1-7 [doi]
• A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet linksJose Fernando Zazo, Sergio López-Buedo, Mario Ruiz, Gustavo Sutter. 1-6 [doi]
• Thorough analysis of PCIe Gen3 communicationHiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku. 1-6 [doi]
• Synchronizing reconfiguration of coherent functions on disaggregated FPGA resourcesQianqiao Chen, Vaibhawa Mishra, Jose Nunez-Yanez, Georgios Zervas. 1-6 [doi]
• Dynamic management of a partial reconfigurable hardware architecture for pedestrian detection in regions of interestMetzli Ramirez-Martinez, Francisco Sanchez-Fernandez, Philippe Brunet, Sidi-Mohammed Senouci, El-Bay Bourennane. 1-7 [doi]
• Autotuning high-level synthesis for FPGAs using OpenTuner and LegUpPedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic. 1-6 [doi]
• Energy-efficient reconfiguration of flash-based FPGAs in heterogeneous wireless sensor nodesAndreas Engel, Andreas Koch. 1-8 [doi]
• Simple CART based real-time traffic classification engine on FPGAsTuncay Soylu, Oguzhan Erdem, Aydin Carus, Edip S. Guner. 1-8 [doi]
• Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLSJan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck. 1-8 [doi]
• H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chipIan J. Barge, Cristinel Ababei. 1-6 [doi]
• An FPGA-based prototyping framework for Networks-on-ChipTobias Drewes, Jan Moritz Joseph, Thilo Pionteck. 1-7 [doi]
• Fine-grained on-line power monitoring for soft microprocessor based system-on-chipYoung H. Cho, Siddharth S. Bhargav. 1-6 [doi]
• Horizontal address-bit DPA against montgomery kP implementationIevgen Kabin, Zoya Dyka, Dan Kreiser, Peter Langendörfer. 1-8 [doi]
• A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasuresAhmad Salman, Ahmed Ferozpuri, Ekawat Homsirikamol, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj. 1-8 [doi]
• Deriving concentrators from binary sorters using half cleanersTripti Jain, Klaus Schneider 0001, Ankesh Jain. 1-6 [doi]
• HW/SW co-design experimental framework using configurable SoCsSiyuan Xu, Jianqi Chen, Benjamin Carrión Schäfer. 1-6 [doi]
• Rapid circuit-specific inlining tuning for FPGA high-level synthesisDaniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton. 1-6 [doi]
• Keynote 2 - FPGA-accelerated high-performance computing - Close to breakthrough or pipedream?Christian Plessi. 1 [doi]
• TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arraysEricles Rodrigues Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich. 1-3 [doi]
• Biologically inspired hierarchical structure for self-repairing FPGAsDavid C. Keezer, Jingchi Yang. 1-8 [doi]
• VHDL generator for a high performance convolutional neural network FPGA-based acceleratorMuhammad K. Hamdan, Diane T. Rover. 1-6 [doi]
• FPGA virtualization with accelerators overcommitment for network function virtualizationMichele Paolino, Sebastien Pinneterre, Daniel Raho. 1-6 [doi]
• An FPGA-based approach for packet deduplication in 100 gigabit-per-second networksMario Ruiz, Gustavo Sutter, Sergio López-Buedo, Jose Fernando Zazo, Jorge E. López de Vergara. 1-6 [doi]
• Aging resilient RO PUF with increased reliability in FPGASreeja Chowdhury, Xiaolin Xu, Mark Tehranipoor, Domenic Forte. 1-7 [doi]
• Synthesis of interleaved multithreaded accelerators from OpenMP loopsLukas Sommer, Julian Oppermann, Jaco Hofmann, Andreas Koch 0001. 1-7 [doi]
• Minerva: Automated hardware optimization toolFarnoud Farahmand, Ahmed Ferozpuri, William Diehl, Kris Gaj. 1-8 [doi]
• Side-channel resistant soft core processor for lightweight block ciphersWilliam Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj. 1-8 [doi]
• Application-specific processing using high-level synthesis for networks-on-chipJens Rettkowski, Diana Göhringer. 1-7 [doi]
• A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arraysEricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich. 1-8 [doi]
• Software defined network controller: A neat solution administration for reconfigurable multi-core NoCIbarra-Delgado Salvador, Sandoval-Arechiga Remberto, Maria Brox, Manuel A. Ortiz. 1-4 [doi]
• Trusted display and input using screen overlaysAnthony Brandon, Michael Trimarchi. 1-6 [doi]
• Keynote 1 - Education is not learning facts, but training the mind to thinkJohn Watson. 1 [doi]
• Microchannels for thermal management in FPGAsGirish Deshpande, Dinesh K. Bhatia. 1-5 [doi]
• Glitch-aware variable pipeline optimization for CGRAsTakuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano. 1-6 [doi]
• Fault tolerance in neural networks: Neural design and hardware implementationCésar Torres-Huitzil, Bernard Girau. 1-6 [doi]
• Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesisAndrew Boutros, Brett Grady, Mustafa Abbas, Paul Chow. 1-6 [doi]
• Designing a collision detection accelerator on a heterogeneous CPU-FPGA platformFredy Augusto M. Alves, Peter Jamieson, Lucas B. da Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif. 1-6 [doi]
• An FPGA-in-the-loop approach for HDL motor controller verificationPaul Rogers, Rajesh Kavasseri, Scott C. Smith. 1-6 [doi]