Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique - researchr publication authors

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Daniel H. Y. Teng, Ronald J. Bolton. Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique. In 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada. pages 276-281, IEEE Computer Society, 2005. [doi]

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