A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model

Georgios Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis. A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. VLSI Design, 2001(1):69-79, 2001. [doi]

@article{TheodoridisTSG01,
  title = {A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model},
  author = {Georgios Theodoridis and Spyros Theoharis and Dimitrios Soudris and Constantinos E. Goutis},
  year = {2001},
  doi = {10.1155/2001/12026},
  url = {https://doi.org/10.1155/2001/12026},
  researchr = {https://researchr.org/publication/TheodoridisTSG01},
  cites = {0},
  citedby = {0},
  journal = {VLSI Design},
  volume = {2001},
  number = {1},
  pages = {69-79},
}