Edward W. Thompson, Stephen A. Szygenda, N. Billawala, R. Pierce. Timing analysis for digital fault simulation using assignable delays. In Herbert M. Wall, Robert B. Hitchcock Sr., Stephen P. Krosner, J. Michael Galey, Nitta P. Dooner, Donald J. Humcke, Pat O. Pistilli, editors, Proceedings of the 11th Design Automation Workshop, DAC '74, Denver, Colorado, USA, June 11-19, 1974. pages 266-272, ACM, 1974. [doi]
Abstract is missing.