Hardware implementation of a high speed self-synchronizing cipher mode

Yuanchi Tian, Howard M. Heys. Hardware implementation of a high speed self-synchronizing cipher mode. In IEEE 28th Canadian Conference on Electrical and Computer Engineering, CCECE 2015, Halifax, NS, Canada, May 3-6, 2015. pages 695-700, IEEE, 2015. [doi]

Abstract

Abstract is missing.