The following publications are possibly variants of this publication:
- A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation DecompositionNozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki. ieicet, 88-D(7):1340-1349, 2005. [doi]
- An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructionsYuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. apccas 2002: 171-176 [doi]
- A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type InstructionsNozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki. ieiceta, 86-A(12):3218-3224, 2003. [doi]
- A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type InstructionsNozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki. ieiceta, 86-A(12):3099-3109, 2003. [doi]