Hardware architecture for lowering the error floor of LTE turbo codes

Thibaud Tonnellier, Camille Leroux, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat, Nicolas Van Wambeke. Hardware architecture for lowering the error floor of LTE turbo codes. In 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, October 12-14, 2016. pages 107-112, IEEE, 2016. [doi]

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