Table of Contents

• Session 1: HEVC in embedded systemsEduardo Juárez. 1 [doi]
• Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoderRonan Parois, Wassim Hamidouche, Elie Gabriel Mora, Mickaël Raulet, Olivier Déforges. 11-17 [doi]
• Scalable HEVC decoder for mobile devices: Trade-off between energy consumption and qualityErwan Raffin, Wassim Hamidouche, Erwan Nogues, Maxime Pelcat, Daniel Ménard. 18-25 [doi]
• Estimating encoding complexity of a real-time embedded software HEVC codecAlexandre Mercat, Wassim Hamidouche, Maxime Pelcat, Daniel Ménard. 26-33 [doi]
• Analysis on scalability and energy efficiency of HEVC decoding using task-based programming modelGeorgios Georgakarakos, Simon Holmbacka, Johan Lilius. 34-41 [doi]
• Session 2: Architectures for image processingFrancesca Palumbo. 42 [doi]
• ELM-based hyperspectral imagery processor for onboard real-time classificationKoldo Basterretxea, Unai Martinez-Corral, Raul Finker, Inés del Campo. 43-50 [doi]
• Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge DetectionRobin Danilo, Hugues Nono Wouafo, Cyrille Chavet, Vincent Gripon, Laura Conde-Canencia, Philippe Coussy. 51-58 [doi]
• Memory efficient Multi-Scale Line Detector architecture for retinal blood vessel segmentationHamza Bendaoudi, Farida Cheriet, J. M. Pierre Langlois. 59-64 [doi]
• SystemC modelling of lossless compression IP cores for space applicationsLucana Santos, Ana Gomez, Pedro Hernandez-Fernandez, Roberto Sarmiento. 65-72 [doi]
• Session 3: Method and tools for system designDiana Goehringer. 73 [doi]
• A system-level security approach for heterogeneous MPSoCsBenjamin Tan, Morteza Biglari-Abhari, Zoran Salcic. 74-81 [doi]
• Low power design methodology for signal processing systems using lightweight dataflow techniquesLin Li, Tiziana Fanni, Timo Viitanen, Renjie Xie, Francesca Palumbo, Luigi Raffo, Heikki Huttunen, Jarmo Takala, Shuvra S. Bhattacharyya. 82-89 [doi]
• Code generation for a SIMD architecture with custom memory organisationMehmet Ali Arslan, Flavius Gruian, Krzysztof Kuchcinski, Andreas Karlsson. 90-97 [doi]
• Fuzzy logic modeling for objective image quality assessmentGhislain Takam Tchendjou, Rshdee Alhakim, Emmanuel Simeu. 98-105 [doi]
• Session 4: Advanced hardware architecturesMorteza Biglari-Abhari. 106 [doi]
• Hardware architecture for lowering the error floor of LTE turbo codesThibaud Tonnellier, Camille Leroux, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat, Nicolas Van Wambeke. 107-112 [doi]
• ARM-FPGA based platform for automated adaptive wireless communication systems using partial reconfiguration techniqueMohamad Alfadl Rihani, Jean-Christophe Prévotet, Fabienne Nouvel, Mohamad Mroué, Yasser Mohanna. 113-120 [doi]
• Crosstalk-aware link power model for Networks-on-ChipErwan Moreac, André Rossi, Johann Laurent, Pierre Bomel. 121-128 [doi]
• Session 5: Image processing on multicore plateformsPierre Langlois. 129 [doi]
• Batched Cholesky factorization for tiny matricesFlorian Lemaitre, Lionel Lacassagne. 130-137 [doi]
• Custom processor design for efficient, yet flexible Lucas-Kanade optical flowSander Smets, Toon Goedemé, Marian Verhelst. 138-145 [doi]
• A pipelined multi-softcore approach for the HOG algorithmJosé Arnaldo Mascagni de Holanda, João Manuel Paiva Cardoso, Eduardo Marques. 146-153 [doi]
• Hyperspectral image classification using a parallel implementation of the linear SVM on a Massively Parallel Processor Array (MPPA) platformD. Madronal, R. Lazcano, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó, E. Juarez, C. Sanz. 154-160 [doi]
• Special session 1 automotive parallel computing challenges - architectures, applications and tricksWalter Stechele, Tomasz Kryjak, Lionel Lacassagne, Dominique Houzet, Martin Danek. 161 [doi]
• Monte Carlo method based precision analysis of deep convolution netsRobert Krutsch, Sharath Naidu. 162-167 [doi]
• Hardware acceleration of Maximum-Likelihood angle estimation for automotive MIMO radarsFrank Meinl, Martin Kunert, Holger Blume. 168-175 [doi]
• FPGA memory optimization for real-time imagingDominique Houzet, Virginie Fresse, Hubert Konik. 176-182 [doi]
• FPGA-based Hardware-in-the-Loop environment using video injection concept for camera-based systems in automotive applicationsMateusz Komorkiewicz, Krzysztof Turek, Pawel Skruch, Tomasz Kryjak, Marek Gorgon. 183-190 [doi]
• Generation of schedule tables on multi-core systems for AUTOSAR applicationsWenhao Wang, Fabrice Camut, Benoit Miramond. 191-198 [doi]
• Special session 2 Computer vision and Image analysisPatrice Delmas, Rachel Ababou, Patrice Delmas. 199 [doi]
• Memory management in embedded vision systems: Optimization problems and solution methodsKhadija Hadj Salem, Yann Kieffer, Stéphane Mancini. 200-207 [doi]
• A comparison of cost construction methods onto a C6678 platform for stereo matchingJudicael Menant, Guillaume Gautier, Jean-François Nezan, Muriel Pressigout, Luce Morin. 208-214 [doi]
• A dedicated lightweight binocular stereo system for real-time depth-map generationTrevor Gee, Patrice Delmas, Sylvain Joly, Valentin Baron, Rachel Ababou, Jean-François Nezan. 215-221 [doi]
• Demo NightPierre Langlois, Kevin J. M. Martin, Eduardo Juárez Martínez. 222 [doi]
• Demo: Localisation in a faulty digital GPS receiverMohamed Mourad Hafidhi, Emmanuel Boutillon, Arnaud Dion. 223-224 [doi]
• Demo: Ker-ONE: Embedded virtualization approach with dynamic reconfigurable accelerators managementTian Xia, Mohamad Alfadl Rihani, Jean-Christophe Prévotet, Fabienne Nouvel. 225-226 [doi]
• Demo: Efficient delay and apodization for on-FPGA 3D ultrasoundA. C. Yuzuguler, W. Simon, A. Ibrahim, Federico Angiolini, M. Arditi, Jean-Philippe Thiran, Giovanni De Micheli. 227-228 [doi]
• Demo abstract: How fuzzy logic can enhance energy management in Wireless Sensor nodes equipped by energy harvesters and wake-up radiosFayçal Ait Aoudia, Matthieu Gautier, Olivier Berder. 229-230 [doi]
• FPGA-based bio-inspired architecture for multi-scale attentional visionNicolas Cuperlier, Frederic de Melo, Benoit Miramond. 231-232 [doi]
• Demo: SLP-aware word length optimizationAli Hassan El Moussawi, Steven Derrien. 233-234 [doi]
• Demo: UHD live video streaming with a real-time scalable HEVC encoderRonan Parois, Wassim Hamidouche, Elie Gabriel Mora, Mickaël Raulet, Olivier Déforges. 235-236 [doi]
• Demo: HELICoiD tool demonstrator for real-time brain cancer detectionR. Salvador, Himar Fabelo, R. Lazcano, Samuel Ortega, D. Madronal, Gustavo Marrero Callicó, E. Juarez, C. Sanz. 237-238 [doi]
• Demo: Overlay architectures for heterogeneous FPGA cluster managementTheotime Bollengier, Mohamad Najem, Jean-Christophe Le Lann, Loïc Lagadec. 239-240 [doi]
• Demo abstract: FPGA-based implementation of a flexible FFT dedicated to LTE standardMai-Thanh Tran, Emmanuel Casseau, Matthieu Gautier. 241-242 [doi]
• ® manycore processor towards future ADAS system solutionsPierre-Edouard Beaucamps, Frédéric Blanc Kalray. 243-244 [doi]
• Demo: Reconfigurable Platform Composer ToolCarlo Sau, Tiziana Fanni, Paolo Meloni, Luigi Raffo, Maxime Pelcat, Francesca Palumbo. 245-246 [doi]