Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications - researchr publication authors

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V. Torres, A. Perez-Pascual, T. Sansaloni, Javier Valls. Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications. VLSI Signal Processing, 56(1):17-23, 2009. [doi]

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