Marc Tremblay, Shailender Chaudhry. A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor. In 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008. pages 82-83, IEEE, 2008. [doi]
@inproceedings{TremblayC08,
title = {A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor},
author = {Marc Tremblay and Shailender Chaudhry},
year = {2008},
doi = {10.1109/ISSCC.2008.4523067},
url = {http://dx.doi.org/10.1109/ISSCC.2008.4523067},
researchr = {https://researchr.org/publication/TremblayC08},
cites = {0},
citedby = {0},
pages = {82-83},
booktitle = {2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008},
publisher = {IEEE},
isbn = {978-1-4244-2010-0},
}