Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU

Minh Thien Trieu, Huong Thien Hoang, Phong The Vo, Hung Bao Vo, Yoichi Yuyama. Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU. In 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011. pages 39-42, IEEE, 2011. [doi]

Abstract

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