False Path and Clock Scheduling Based Yield-Aware Gate Sizing

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja. False Path and Clock Scheduling Based Yield-Aware Gate Sizing. In 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India. pages 423-426, IEEE Computer Society, 2005. [doi]

Abstract

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