Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski. 14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015. pages 1-3, IEEE, 2015. [doi]
@inproceedings{TsaiYCLLS15,
title = {14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S},
author = {Tsung-Hsien Tsai and Min-Shueh Yuan and Chih-Hsien Chang and Chia-Chun Liao and Chao-Chieh Li and Robert Bogdan Staszewski},
year = {2015},
doi = {10.1109/ISSCC.2015.7063025},
url = {http://dx.doi.org/10.1109/ISSCC.2015.7063025},
researchr = {https://researchr.org/publication/TsaiYCLLS15},
cites = {0},
citedby = {0},
pages = {1-3},
booktitle = {2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015},
publisher = {IEEE},
isbn = {978-1-4799-6224-2},
}