Tzu-Ting Tseng, Chung-An Shen. The VLSI architecture of a highly efficient configurable pre-processor for MIMO detections. In 36th IEEE International Performance Computing and Communications Conference, IPCCC 2017, San Diego, CA, USA, December 10-12, 2017. pages 1-5, IEEE, 2017. [doi]
@inproceedings{TsengS17-0,
title = {The VLSI architecture of a highly efficient configurable pre-processor for MIMO detections},
author = {Tzu-Ting Tseng and Chung-An Shen},
year = {2017},
doi = {10.1109/PCCC.2017.8280499},
url = {https://doi.org/10.1109/PCCC.2017.8280499},
researchr = {https://researchr.org/publication/TsengS17-0},
cites = {0},
citedby = {0},
pages = {1-5},
booktitle = {36th IEEE International Performance Computing and Communications Conference, IPCCC 2017, San Diego, CA, USA, December 10-12, 2017},
publisher = {IEEE},
isbn = {978-1-5090-6468-7},
}