Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera. Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Transactions, 88-A(4):885-891, 2005. [doi]

@article{TsuchiyaHO05:0,
  title = {Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling},
  author = {Akira Tsuchiya and Masanori Hashimoto and Hidetoshi Onodera},
  year = {2005},
  doi = {10.1093/ietfec/e88-a.4.885},
  url = {http://dx.doi.org/10.1093/ietfec/e88-a.4.885},
  researchr = {https://researchr.org/publication/TsuchiyaHO05%3A0},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {88-A},
  number = {4},
  pages = {885-891},
}