Divyasree Tummalapalli, Kunapareddy Chiranjeevi, Vikas Akalwadi, Rahul Govindan, Balaji G. Novel Design partitioning technique for ASIC prototyping on multi-FPGA platforms using Graph Deep Learning. In 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, United Kingdom, October 24-26, 2022. pages 1-4, IEEE, 2022. [doi]
Abstract is missing.