A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders

Georgios Tzimpragos, Christoforos Kachris, Dimitrios Soudris, Ioannis Tomkos. A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders. In 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, Phoenix, AZ, USA, May 19-23, 2014. pages 269-274, IEEE, 2014. [doi]

@inproceedings{TzimpragosKST14,
  title = {A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders},
  author = {Georgios Tzimpragos and Christoforos Kachris and Dimitrios Soudris and Ioannis Tomkos},
  year = {2014},
  doi = {10.1109/IPDPSW.2014.36},
  url = {http://dx.doi.org/10.1109/IPDPSW.2014.36},
  researchr = {https://researchr.org/publication/TzimpragosKST14},
  cites = {0},
  citedby = {0},
  pages = {269-274},
  booktitle = {2014 IEEE International Parallel & Distributed Processing Symposium Workshops, Phoenix, AZ, USA, May 19-23, 2014},
  publisher = {IEEE},
  isbn = {978-0-7695-5208-8},
}