Yeong-Luh Ueng, Chung-Jay Yang, Zong-Cheng Wu, Chen-Eng Wu, Yu-Lun Wang. VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA. pages 520-523, IEEE, 2008. [doi]
@inproceedings{UengYWWW08,
title = {VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX},
author = {Yeong-Luh Ueng and Chung-Jay Yang and Zong-Cheng Wu and Chen-Eng Wu and Yu-Lun Wang},
year = {2008},
doi = {10.1109/ISCAS.2008.4541469},
url = {http://dx.doi.org/10.1109/ISCAS.2008.4541469},
tags = {architecture},
researchr = {https://researchr.org/publication/UengYWWW08},
cites = {0},
citedby = {0},
pages = {520-523},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA},
publisher = {IEEE},
}