VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX

Yeong-Luh Ueng, Chung-Jay Yang, Zong-Cheng Wu, Chen-Eng Wu, Yu-Lun Wang. VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX. In International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA. pages 520-523, IEEE, 2008. [doi]

Abstract

Abstract is missing.