The following publications are possibly variants of this publication:
- A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode ImplementationRei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki. ches 2016: 538-558 [doi]
- High Throughput/Gate AES Hardware Architectures Based on Datapath CompressionRei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger. TC, 69(4):534-548, 2020. [doi]