Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs

Anees Ullah, Luca Sterpone. Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. J. Electronic Testing, 30(4):425-442, 2014. [doi]

Authors

Anees Ullah

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Luca Sterpone

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