The following publications are possibly variants of this publication:
- Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory SystemsGanesan Umanesan, Eiji Fujiwara. dft 2000: 192-200 [doi]
- Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory SystemsGanesan Umanesan, Eiji Fujiwara. ieiceta, 85-A(2):513-517, 2002. [doi]
- Single ::::b::::-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory SystemsEiji Fujiwara, Mitsuru Hamada. ftcs 1992: 494-501
- Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory SystemsShigeo Kaneda, Eiji Fujiwara. TC, 31(7):596-602, 1982.
- A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) CodesGanesan Umanesan, Eiji Fujiwara. TC, 52(7):835-847, 2003. [doi]