A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM - researchr publication authors

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Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii. A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. IPSJ T. on System LSI Design Methodology, 9:79-83, 2016. [doi]

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