Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit

Masayuki Uno, Shoji Kawahito. Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit. IEICE Transactions, 89-C(6):702-709, 2006. [doi]

@article{UnoK06,
  title = {Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit},
  author = {Masayuki Uno and Shoji Kawahito},
  year = {2006},
  doi = {10.1093/ietele/e89-c.6.702},
  url = {http://dx.doi.org/10.1093/ietele/e89-c.6.702},
  tags = {design},
  researchr = {https://researchr.org/publication/UnoK06},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {89-C},
  number = {6},
  pages = {702-709},
}