Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi. Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. In IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021, Tokyo, Japan, April 14-16, 2021. pages 1-3, IEEE, 2021. [doi]
@inproceedings{UrabeOK21,
title = {Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT},
author = {Takaki Urabe and Hiroyuki Ochi and Kazutoshi Kobayashi},
year = {2021},
doi = {10.1109/COOLCHIPS52128.2021.9410314},
url = {https://doi.org/10.1109/COOLCHIPS52128.2021.9410314},
researchr = {https://researchr.org/publication/UrabeOK21},
cites = {0},
citedby = {0},
pages = {1-3},
booktitle = {IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021, Tokyo, Japan, April 14-16, 2021},
publisher = {IEEE},
isbn = {978-1-6654-1503-3},
}