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An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design

C. Uttraphan, Nasir Shaikh-Husin, Mohamed Khalil Hani. An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design. In Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014. pages 357-364, IEEE, 2014. [doi]

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