Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction - researchr publication authors

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Alexandre Valentian, Edith Beigné. Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction. In Doris Schmitt-Landsiedel, Tobias Noll, editors, 33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007. pages 300-303, IEEE, 2007. [doi]

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