A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop

Socrates D. Vamvakos, Charles Boecker, Eric Groen, Alvin Wang, Shaishav Desai, Scott Irwin, Vithal Rao, Aldo Bottelli, Jawji Chen, Xiaole Chen, Prashant Choudhary, Kuo-Chiang Hsieh, Paul Jennings, Haidang Lin, Dan Pechiu, Chethan Rao, Jason Yeung. A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014. pages 1-4, IEEE, 2014. [doi]

Authors

Socrates D. Vamvakos

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Charles Boecker

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Eric Groen

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Alvin Wang

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Shaishav Desai

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Scott Irwin

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Vithal Rao

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Aldo Bottelli

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Jawji Chen

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Xiaole Chen

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Prashant Choudhary

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Kuo-Chiang Hsieh

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Paul Jennings

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Haidang Lin

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Dan Pechiu

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Chethan Rao

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Jason Yeung

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