An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis

Sayyaparaju Sagar Varma, Arvind Sharma, Bulusu Anand. An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis. In 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016, Lisbon, Portugal, June 27-30, 2016. pages 1-4, IEEE, 2016. [doi]

Abstract

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