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A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET

Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos. A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 26-27, IEEE, 2022. [doi]

Authors

Aida Varzaghani

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Bardia Bozorgzadeh

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Jack Lam

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Ankush Goel

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Xiaobin Yuan

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Mohamed Elzeftawi

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Mehran Izad

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Sudipta Sarkar

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Alberto Baldisserotto

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Seong-Ryong Ryu

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Steven Mikes

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Jeffrey Hwang

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Varun Joshi

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Shahrzad Naraghi

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Darshan Kadia

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Mohammad Ranjbar

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Paul Lee

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Dimitri Loizos

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Sotirios Zogopoulos

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Shwetabh Verma

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Stefanos Sidiropoulos

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