A Parallel Algorithm for Bayesian Network Inference Using Arithmetic Circuits

Md. Vasimuddin, Sriram P. Chockalingam, Srinivas Aluru. A Parallel Algorithm for Bayesian Network Inference Using Arithmetic Circuits. In 2018 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2018, Vancouver, BC, Canada, May 21-25, 2018. pages 34-43, IEEE Computer Society, 2018. [doi]

@inproceedings{VasimuddinCA18,
  title = {A Parallel Algorithm for Bayesian Network Inference Using Arithmetic Circuits},
  author = {Md. Vasimuddin and Sriram P. Chockalingam and Srinivas Aluru},
  year = {2018},
  doi = {10.1109/IPDPS.2018.00014},
  url = {http://doi.ieeecomputersociety.org/10.1109/IPDPS.2018.00014},
  researchr = {https://researchr.org/publication/VasimuddinCA18},
  cites = {0},
  citedby = {0},
  pages = {34-43},
  booktitle = {2018 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2018, Vancouver, BC, Canada, May 21-25, 2018},
  publisher = {IEEE Computer Society},
  isbn = {978-1-5386-4368-6},
}