Madhava Sarma Vemuri, Tanvir Ahmed, Umamaheswara Rao Tida. Compact 6T-SRAM Using Bottom-Gate Transistor in FD-SOI Process for Monolithic-3D Integration. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2024, Knoxville, TN, USA, July 1-3, 2024. pages 725-729, IEEE, 2024. [doi]
Abstract is missing.