Deep Neural Network Training Accelerator Designs in ASIC and FPGA

Shreyas K. Venkataramanaiah, Shihui Yin, Yu Cao 0001, Jae-sun Seo. Deep Neural Network Training Accelerator Designs in ASIC and FPGA. In International SoC Design Conference, ISOCC 2020, Yeosu, South Korea, October 21-24, 2020. pages 21-22, IEEE, 2020. [doi]

Abstract

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