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Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage

Praveen Venkataramani, Vishwani D. Agrawal. Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 273-278, IEEE, 2013. [doi]

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