Natesan Venkateswaran, Dinesh Bhatia. Clock-Skew Constrained Cell Placement. In 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India. pages 146-149, IEEE Computer Society, 1996. [doi]
@inproceedings{VenkateswaranB96,
title = {Clock-Skew Constrained Cell Placement},
author = {Natesan Venkateswaran and Dinesh Bhatia},
year = {1996},
doi = {10.1109/ICVD.1996.489474},
url = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1996.489474},
researchr = {https://researchr.org/publication/VenkateswaranB96},
cites = {0},
citedby = {0},
pages = {146-149},
booktitle = {9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India},
publisher = {IEEE Computer Society},
}