Vishak Venkatraman, Wayne Burleson. Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects. In 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India. pages 362-367, IEEE Computer Society, 2005. [doi]
@inproceedings{VenkatramanB05:0,
title = {Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects},
author = {Vishak Venkatraman and Wayne Burleson},
year = {2005},
url = {http://csdl.computer.org/comp/proceedings/vlsid/2005/2264/00/22640362abs.htm},
researchr = {https://researchr.org/publication/VenkatramanB05%3A0},
cites = {0},
citedby = {0},
pages = {362-367},
booktitle = {18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2264-5},
}