Anselme Vignon, Stefan Cosemans, Wim Dehaene, Pol Marchal, Marco Facchini. A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009. pages 929-933, IEEE, 2009. [doi]
@inproceedings{VignonCDMF09,
title = {A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context},
author = {Anselme Vignon and Stefan Cosemans and Wim Dehaene and Pol Marchal and Marco Facchini},
year = {2009},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=5090609&arnumber=5090798&count=326&index=184},
tags = {caching, architecture, context-aware},
researchr = {https://researchr.org/publication/VignonCDMF09},
cites = {0},
citedby = {0},
pages = {929-933},
booktitle = {Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009},
publisher = {IEEE},
}