Circuit level, 32nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier

S. Vijayakumar, Reeba Korah. Circuit level, 32nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier. IEICE Electronic Express, 11(6):20140109, 2014. [doi]

@article{VijayakumarK14,
  title = {Circuit level, 32nm, 1-bit MOSSI-ULP adder: power, PDP and area efficient base cell for unsigned multiplier},
  author = {S. Vijayakumar and Reeba Korah},
  year = {2014},
  doi = {10.1587/elex.11.20140109},
  url = {http://dx.doi.org/10.1587/elex.11.20140109},
  researchr = {https://researchr.org/publication/VijayakumarK14},
  cites = {0},
  citedby = {0},
  journal = {IEICE Electronic Express},
  volume = {11},
  number = {6},
  pages = {20140109},
}