TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs - researchr publication

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Sahu Sai Vikram, Vibha Panty, Mihir Mody, Madhura Purnaprajna. TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. In 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018. pages 461-462, IEEE Computer Society, 2018. [doi]

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