R. A. Wachnik, S. Lee, L. H. Pan, N. Lu, H. Li, R. Bingert, M. Randall, S. Springer, C. Putnam. Gate stack resistance and limits to CMOS logic performance. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, September 22-25, 2013. pages 1-4, IEEE, 2013. [doi]
Abstract is missing.