A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS

Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak. A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. In 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016. pages 236-239, IEEE Computer Society, 2016. [doi]

@inproceedings{WadekarCMN16,
  title = {A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS},
  author = {Jayesh Wadekar and Biman Chattopadhyay and Ravi Mehta and Gopalkrishna Nayak},
  year = {2016},
  doi = {10.1109/VLSID.2016.90},
  url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2016.90},
  researchr = {https://researchr.org/publication/WadekarCMN16},
  cites = {0},
  citedby = {0},
  pages = {236-239},
  booktitle = {29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016},
  publisher = {IEEE Computer Society},
  isbn = {978-1-4673-8700-2},
}