24-bit significand multiplier for FPGA floating-point multiplication

E. George Walters. 24-bit significand multiplier for FPGA floating-point multiplication. In Michael B. Matthews, editor, 49th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015, Pacific Grove, CA, USA, November 8-11, 2015. pages 717-721, IEEE, 2015. [doi]

Abstract

Abstract is missing.