FastLane: improving performance of software transactional memory for low thread counts

Jons-Tobias Wamhoff, Christof Fetzer, Pascal Felber, Etienne Rivière, Gilles Muller. FastLane: improving performance of software transactional memory for low thread counts. In Alex Nicolau, Xiaowei Shen, Saman P. Amarasinghe, Richard Vuduc, editors, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP '13, Shenzhen, China, February 23-27, 2013. pages 113-122, ACM, 2013. [doi]

Abstract

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