A New Validation Methodology Combining Test and Formal Verification for PowerPC:::TM::: Microprocessor Arrays

Li-C. Wang, Magdy S. Abadir. A New Validation Methodology Combining Test and Formal Verification for PowerPC:::TM::: Microprocessor Arrays. In Proceedings IEEE International Test Conference 1997, Washington, DC, USA, November 3-5, 1997. pages 954-963, IEEE Computer Society, 1997.

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.