The following publications are possibly variants of this publication:
- Fraction Control Bus: A New SoC On-chip Communication Architecture DesignNan Wang, Magdy A. Bayoumi. csreaESA 2005: 124-129
- System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologiesNan Wang, Magdy A. Bayoumi. iet-cdt, 1(1):1-8, 2007. [doi]
- Reconfigurable Global Network Local Bus (RGNLS): A Hybrid On-Chip Communication Architecture for Area-Efficient, Dynamically Reconfigurable SoC DesignsLing Wang, Feng Wu, Jianwen Zhang, Yingtao Jiang. csreaESA 2009: 211-217
- An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level DesignYawen Niu, Jinian Bian, Haili Wang, Kun Tong. cscwd 2007: 118-127 [doi]