Chifeng Wang, Nader Bagherzadeh. Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip. Microprocessors and Microsystems, 38(4):304-315, 2014. [doi]
@article{WangB14-3,
title = {Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip},
author = {Chifeng Wang and Nader Bagherzadeh},
year = {2014},
doi = {10.1016/j.micpro.2013.09.006},
url = {http://dx.doi.org/10.1016/j.micpro.2013.09.006},
researchr = {https://researchr.org/publication/WangB14-3},
cites = {0},
citedby = {0},
journal = {Microprocessors and Microsystems},
volume = {38},
number = {4},
pages = {304-315},
}