Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

Chifeng Wang, Nader Bagherzadeh. Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip. Microprocessors and Microsystems, 38(4):304-315, 2014. [doi]

Abstract

Abstract is missing.