PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning

Zixiao Wang, Biyao Che, Liang Guo 0003, Yang Du, Ying Chen, Jizhuang Zhao, Wei He 0015. PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning. IEEE Access, 10:98649-98661, 2022. [doi]

Abstract

Abstract is missing.