Design of Psub-SMPD and DNW-SMPD fabricated in a standard 0.18-µm CMOS process

Rong Wang, Chen Fan, Zhi-Gong Wang. Design of Psub-SMPD and DNW-SMPD fabricated in a standard 0.18-µm CMOS process. IEICE Electronic Express, 14(14):20170611, 2017. [doi]

@article{WangFW17-2,
  title = {Design of Psub-SMPD and DNW-SMPD fabricated in a standard 0.18-µm CMOS process},
  author = {Rong Wang and Chen Fan and Zhi-Gong Wang},
  year = {2017},
  doi = {10.1587/elex.14.20170611},
  url = {https://doi.org/10.1587/elex.14.20170611},
  researchr = {https://researchr.org/publication/WangFW17-2},
  cites = {0},
  citedby = {0},
  journal = {IEICE Electronic Express},
  volume = {14},
  number = {14},
  pages = {20170611},
}